US 12,308,331 B2
Via structure for semiconductor dies
Yaoyu Pang, Austin, TX (US); and Steven A. Atherton, Austin, TX (US)
Assigned to Cirrus Logic Inc., Austin, TX (US)
Filed by Cirrus Logic International Semiconductor Ltd., Edinburgh (GB)
Filed on May 19, 2022, as Appl. No. 17/748,817.
Application 17/748,817 is a division of application No. 16/857,606, filed on Apr. 24, 2020, granted, now 11,373,968.
Claims priority of provisional application 62/839,066, filed on Apr. 26, 2019.
Prior Publication US 2022/0285299 A1, Sep. 8, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/52 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 2224/03011 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05559 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05572 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor die, comprising:
forming a polymer layer on a redistribution layer of a semiconductor die,
drilling the polymer layer to provide a plurality of vias through the polymer layer to the redistribution layer such that the plurality of vias are centered on a point not central to an Under Bump Metallurgy (UBM) layer; and
depositing the UBM layer onto the polymer layer such that the plurality of vias electrically couple the UBM layer to the redistribution layer.