| CPC H01L 23/53223 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01)] | 8 Claims |

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1. A semiconductor device, comprising:
a substrate;
multi-level interconnections disposed on the substrate;
a first passivation layer containing a hydrogen rich layer and covering top interconnections among the multi-level interconnections;
a second passivation layer disposed over the first passivation layer to prevent out-diffusion of hydrogen from the first passivation layer;
an in-line top dielectric layer over the second passivation layer;
a hydrogen blocking liner disposed on a sidewall of a through-hole spanning the in-line top dielectric layer, the second passivation layer, and the first passivation layer;
an in-line redistribution layer connected to one among the top interconnections through the through-hole with the hydrogen blocking liner formed on the sidewall thereof; and
wherein the substrate includes a device layer having an interface passivated by hydrogen diffused from the first passivation layer,
wherein the second passivation layer is disposed over the first passivation layer and the device layer,
wherein the hydrogen blocking liner includes an insulation material.
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