US 12,308,313 B2
Semiconductor package with improved interposer structure
Yi-Wen Wu, New Taipei (TW); Techi Wong, Zhubei (TW); Po-Hao Tsai, Zhongli (TW); Po-Yao Chuang, Hsin-Chu (TW); Shih-Ting Hung, New Taipei (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,491.
Application 18/358,491 is a continuation of application No. 17/400,729, filed on Aug. 12, 2021, granted, now 11,848,265.
Application 17/400,729 is a continuation of application No. 16/406,600, filed on May 8, 2019, granted, now 11,094,625, issued on Aug. 17, 2021.
Claims priority of provisional application 62/787,493, filed on Jan. 2, 2019.
Prior Publication US 2023/0378055 A1, Nov. 23, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/96 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/73203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a redistribution structure;
a semiconductor die disposed over the redistribution structure; and
an interposer structure connected to the redistribution structure through connectors, wherein the interposer structure comprises:
an insulating base having a first surface facing the semiconductor die and a second surface opposite to the first surface;
conductive features formed over the insulating base, wherein the conductive features comprises:
first portions formed on the first surface of the insulating base and vertically overlapping the semiconductor die, wherein the first portions are laterally separated from each other and are vertically spaced apart from the semiconductor die;
second portions formed on the first surface of the insulating base and located outside a projection area of the semiconductor die in a top view;
third portions formed on the second surface of the insulating base and vertically overlapping the semiconductor die; and
fourth portions formed on the second surface of the insulating base and located outside the projection area of the semiconductor die in the top view;
capping layers covering the first portions of the conductive features; and
dielectric features in contact with the capping layers and vertically overlapping the semiconductor die.