US 12,308,312 B2
Interconnect structure and method for manufacturing the interconnect structure
Khaderbad Mrunal Abhijith, Hsinchu (TW); Yu-Yun Peng, Hsinchu (TW); Fu-Ting Yen, Hsinchu (TW); Chen-Han Wang, Hsinchu County (TW); Tsu-Hsiu Perng, Hsinchu County (TW); and Keng-Chu Lin, Ping-Tung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Apr. 24, 2023, as Appl. No. 18/305,528.
Application 17/676,719 is a division of application No. 16/884,925, filed on May 27, 2020, granted, now 11,257,753, issued on Feb. 22, 2022.
Application 18/305,528 is a continuation of application No. 17/676,719, filed on Feb. 21, 2022, granted, now 11,637,062.
Claims priority of provisional application 62/963,918, filed on Jan. 21, 2020.
Prior Publication US 2023/0268268 A1, Aug. 24, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76819 (2013.01); H01L 21/76826 (2013.01); H01L 21/76877 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An interconnect structure, comprising:
a substrate having a conductive region adjacent to a gate structure;
a contact over the conductive region;
a first interlayer dielectric (ILD) layer laterally surrounding the contact;
a via connecting a top surface of the contact and the gate structure;
a densified dielectric layer laterally surrounding the via, wherein the densified dielectric layer has a first density, and a sidewall of the via is continuously surrounded by the densified dielectric layer; and
a second ILD layer over the first ILD layer and laterally surrounding an upper portion of the via, wherein the second ILD layer has a second density, the first density is greater than a second density.