US 12,308,271 B2
Semiconductor wafer processing system and method
Kai-Hung Hsiao, Kaohsiung (TW); Chi-Chung Jen, Kaohsiung (TW); Yu-Chun Shen, Tainan (TW); Jhang-Jie Jian, Tainan (TW); and Wen-Chih Chiang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed on Feb. 12, 2024, as Appl. No. 18/439,420.
Application 18/439,420 is a division of application No. 17/463,846, filed on Sep. 1, 2021, granted, now 11,901,207.
Claims priority of provisional application 63/212,506, filed on Jun. 18, 2021.
Prior Publication US 2024/0258145 A1, Aug. 1, 2024
Int. Cl. H01L 21/677 (2006.01); H01L 21/673 (2006.01); H05F 3/00 (2006.01); B25J 11/00 (2006.01)
CPC H01L 21/67733 (2013.01) [H01L 21/6732 (2013.01); H05F 3/00 (2013.01); B25J 11/0095 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
detecting whether a first charge at a conductor electrically coupled to a wafer shelf of a wafer carrier is greater than a second charge at a stocker contact of a discharge circuit;
closing a first conductive path from the conductor to the stocker contact when the first charge is greater than the second charge;
determining whether a third charge at a wafer carrier transport tool is less than a fourth charge at the conductor; and
closing a second conductive path from the conductor to the wafer carrier transport tool when the third charge is less than the fourth charge.