US 12,308,233 B2
Dual critical dimension patterning
Kuo-Chang Kau, Yuanli Township (TW); Wen-Yun Wang, Taipei (TW); Chia-Chu Liu, Shin-Chu (TW); and Hua-Tai Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 8, 2021, as Appl. No. 17/370,382.
Claims priority of provisional application 63/172,962, filed on Apr. 9, 2021.
Prior Publication US 2022/0328304 A1, Oct. 13, 2022
Int. Cl. H01L 21/027 (2006.01); G03F 1/26 (2012.01); G03F 1/38 (2012.01); H01L 21/033 (2006.01)
CPC H01L 21/0274 (2013.01) [G03F 1/26 (2013.01); G03F 1/38 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A patterning process performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness, the patterning process comprising:
performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area;
performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and
performing trim etching to trim the middle layer in the target area.