US 12,308,230 B2
High electron mobility transistor (HEMT) having an indium-containing layer and method of manufacturing the same
Po-Chun Liu, Hsinchu (TW); Chung-Chieh Hsu, Hsinchu (TW); Chi-Ming Chen, Hsinchu (TW); Chung-Yi Yu, Hsinchu (TW); Chen-Hao Chiang, Hsinchu (TW); and Min-Chang Ching, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 9, 2023, as Appl. No. 18/151,972.
Application 18/151,972 is a continuation of application No. 17/089,147, filed on Nov. 4, 2020, granted, now 11,551,927.
Application 17/089,147 is a continuation of application No. 14/182,847, filed on Feb. 18, 2014, granted, now 10,867,792, issued on Dec. 15, 2020.
Prior Publication US 2023/0162976 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/201 (2006.01); H01L 29/205 (2006.01); H01L 29/207 (2006.01)
CPC H01L 21/0254 (2013.01) [H01L 21/02458 (2013.01); H01L 21/0251 (2013.01); H01L 21/0262 (2013.01); H01L 29/454 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01); H01L 29/201 (2013.01); H01L 29/205 (2013.01); H01L 29/207 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A high electron mobility transistor (HEMT) comprising:
a substrate;
a first semiconductor layer over the substrate;
a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, a thickness of the second semiconductor layer ranges from about 1 nanometer (nm) to about 3 nm, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium;
a top layer over the second semiconductor layer;
a gate electrode over the top layer; and
a source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain; and
a diffused region in the top layer, wherein the diffused region comprises a material of the source, the diffused region extends through less than an entirety of the top layer in a thickness direction, and an entirety of the diffused region is closer to the substrate than the gate electrode.