US 12,308,220 B2
Wafer placement table
Tatsuya Kuno, Nagoya (JP); and Seiya Inoue, Handa (JP)
Assigned to NGK INSULATORS, LTD., Nagoya (JP)
Filed by NGK Insulators, Ltd., Nagoya (JP)
Filed on Mar. 7, 2023, as Appl. No. 18/179,490.
Application 18/179,490 is a continuation of application No. PCT/JP2022/035900, filed on Sep. 27, 2022.
Prior Publication US 2024/0105428 A1, Mar. 28, 2024
Int. Cl. H01T 23/00 (2006.01); H01J 37/32 (2006.01)
CPC H01J 37/32724 (2013.01) [H01J 37/32807 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A wafer placement table comprising:
a ceramic plate having a wafer placement surface at an upper surface thereof and containing an electrode therein, the wafer placement surface being a surface on which a wafer can be placed;
a cooling plate made of a metal-ceramic composite and having a cooling medium passage; and
a joining layer configured to join the ceramic plate to the cooling plate,
wherein a distance from the wafer placement surface to at least one of upper base or lower base of the cooling medium passage is not constant throughout a length of the cooling medium passage but varies; and
the cooling plate has a plurality of plate portions including a first plate portion and a second plate portion, and has a structure in which the plurality of plate portions metal-joined to each other,
the first plate portion having a first passage portion which is a through groove provided to have the same shape as the cooling medium passage in plan view, and
the second plate portion having a second passage portion which is a bottomed groove disposed in at least part of a region facing the first passage portion.