| CPC H01J 37/32495 (2013.01) [C23C 16/45565 (2013.01); H01J 37/3244 (2013.01); H01J 37/32623 (2013.01); H01J 37/32091 (2013.01); H01J 37/3255 (2013.01)] | 20 Claims |

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1. A method for creating a high impedance path for reducing parasitic plasma in a process chamber including an electrode and a conducting structure, the method comprising:
selecting a pair of layers to arrange between the electrode and a first surface of the conducting structure;
selecting respective sizes of (i) a first gap between the electrode and a first one of the pair of layers, (ii) a second gap between the pair of layers, and (iii) a third gap between a second one of the pair of layers and the first surface,
wherein selecting the respective sizes includes selecting the respective sizes to prevent parasitic plasma between the first surface and the electrode during a semiconductor process performed in the process chamber; and
arranging the pair of layers between the electrode and the first surface of the conducting structure in accordance with the selected respective sizes of the first gap, the second gap, and the third gap, wherein diameters of each of the pair of layers decrease as a distance increases between the electrode and a respective one of the pair of layers.
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