US 12,308,090 B2
Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters
Dean D. Gans, Nampa, ID (US); and Daniel C. Skinner, Meridian, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jan. 3, 2024, as Appl. No. 18/403,480.
Application 18/403,480 is a continuation of application No. 18/157,945, filed on Jan. 23, 2023, granted, now 11,901,037.
Application 18/157,945 is a continuation of application No. 17/301,531, filed on Apr. 6, 2021, granted, now 11,568,906, issued on Jan. 31, 2023.
Application 17/301,531 is a continuation of application No. 16/853,917, filed on Apr. 21, 2020, granted, now 10,978,115, issued on Apr. 13, 2021.
Application 16/853,917 is a continuation of application No. 16/513,431, filed on Jul. 16, 2019, granted, now 10,629,245, issued on Apr. 21, 2020.
Application 16/513,431 is a continuation of application No. 16/222,806, filed on Dec. 17, 2018, granted, now 10,424,351, issued on Sep. 24, 2019.
Application 16/222,806 is a continuation of application No. 15/933,167, filed on Mar. 22, 2018, granted, now 10,157,647, issued on Dec. 18, 2018.
Application 15/933,167 is a continuation of application No. 14/247,129, filed on Apr. 7, 2014, granted, now 9,934,831, issued on Apr. 3, 2018.
Prior Publication US 2024/0249754 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1045 (2013.01) [G11C 7/109 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first mode register comprising:
a first register, and
a second register,
a second mode register comprising:
a third register configured to store a first control parameter used to select between the first and second registers, and
a fourth register configured to store a second control parameter used to select between the first and second registers; and
a control logic circuit coupled to the first mode register and the second mode register;
wherein the control logic circuit is configured to:
select the first register for writing a first parameter code when the first control parameter indicates the first register, and
select the second register for writing a second parameter code when the first control parameter indicates the second register; and
wherein the control logic circuit is further configured to:
set a first memory operating condition based, at least in part, on the first parameter code when the second control parameter indicates the first register, and
set a second memory operating condition based, at least in part, on the second parameter code when the second control parameter indicates the second register.