| CPC G11C 29/38 (2013.01) [G11C 29/12005 (2013.01)] | 16 Claims |
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12. A method, comprising:
generating a write data signal to a first pin of a memory device;
generating a glitch signal and a control signal to a second pin of the memory device;
latching data from the write data signal for a write operation in response to at least one of the glitch signal and the control signal;
performing a read operation to generate a read data signal; and
determining, based on write data signal, whether bits of the read data signal are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the glitch signal,
wherein when the bits of the read data signal are moved toward a first side, compared with the write data signal, at least one mismatched bit between the read data signal and the write data signal has a logic high value.
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