CPC G11C 29/1201 (2013.01) [G11C 29/18 (2013.01); G11C 29/36 (2013.01); G11C 2029/3602 (2013.01)] | 6 Claims |
1. A reconfigurable MBIST method based on an adaptive March algorithm, comprising:
inserting, after a first read operation of testing steps for sequentially reading and writing storage units in a classic March C+ testing algorithm, Hammer testing algorithm elements which are defined as {↓(w0,r0n,r0); ↓(w1,r1n,r1)}, where ↓(w0,r0n,r0) represents an execution of operations on writing 0, reading 0 n times, reading 0 for the storage units in a memory according to a descending order of addresses, ↓(w1,r1n,r1) represents an execution of operations on writing 1, reading 1 n times, reading 1 for the storage units in the memory according to the descending order of the addresses, and a set value for n is configured according to user-defined instructions;
determining, by comparing PVT parameters with a fault model library, fault prone types under current PVT parameters, selecting a March algorithm that covers the fault prone types under the current PVT parameters, and generating algorithm element selection signals for reconfiguring the March algorithm;
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w1,r1); ↑(r1,w0,r0); ↓(r0,w1,r1); ↓(r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals merely select testing elements of the March C+ testing algorithm, where ↑↓(w0) represents an execution of operations on writing 0 for the storage units in the memory according to an ascending order or the descending order of the addresses; ↑(r0,w1,r1) represents an execution of operations on reading 0, writing 1, reading 1 for the storage units in the memory according to the ascending order of the addresses; ↑(r1,w0,r0) represents an execution of operations on reading 1, writing 0, reading 0 for the storage units in the memory according to the ascending order of the addresses; ↓(r0,w1,r1) represents an execution of operations on reading 0, writing 1, reading 1 for the storage units in the memory according to the descending order of the addresses; ↓(r1,w0,r0) represents an execution of operations on reading 1, writing 0, reading 0 for the storage units in the memory according to the descending order of the addresses; and ↑↓(r0) represents an execution of operations on reading 0 for the storage units in the memory according to the ascending order or the descending order of the addresses;
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w0,r0,r0,w1,r1); ↑(r1,w1,r1,r1,w0,r0); ↓(r0,w0,r0,r0,w1,r1); ↓(r1,w1,r1,r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals select all testing elements and the set value for n is 1, where ↑↓(w0) represents an execution of operations on writing 0 for the storage units in the memory according to the ascending order or the descending order of the addresses; ↑(r0,w0,r0,r0,w1,r1) represents an execution of operations on reading 0, writing 0, reading 0, reading 0, writing 1, reading 1 for the storage units in the memory according to the ascending order of the addresses; ↑(r1,w1,r1,r1,w0,r0) represents an execution of operations on reading 1, writing 1, reading 1, reading 1, writing 0, reading 0 for the storage units in the memory according to the ascending order of the addresses; ↓(r0,w0,r0,r0,w1,r1) represents an execution of operations on reading 0, writing 0, reading 0, reading 0, writing 1, reading 1 for the storage units in the memory according to the descending order of the addresses; ↓(r1,w1,r1,r1,w0,r0) represents an execution of operations on reading 1, writing 1, reading 1, reading 1, writing 0, reading 0 for the storage units in the memory according to the descending order of the addresses; ↑↓(r0) represents an execution of operations on reading 0 for the storage units in the memory according to the ascending order or the descending order of the addresses; and
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w0,r0,r0,w1,r1); ↑(r1,w1,r1,r1,w0,r0); ↓(r0,w0,r0n,r0,w1,r1); ↓(r1,w1,r1n,r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals select all testing elements and the set value for n is greater than 1, where ↑↓(w0) represents an execution of operations on writing 0 for the storage units in the memory according to the ascending order or the descending order of the addresses; ↑(r0,w0,r0,r0,w1,r1) represents an execution of operations on reading 0, writing 0, reading 0, reading 0, writing 1, reading 1 for the storage units in the memory according to the ascending order of the addresses; ↑(r1,w1,r1,r1,w0,r0) represents an execution of operations on reading 1, writing 1, reading 1, reading 1, writing 0, reading 0 for the storage units in the memory according to the ascending order of the addresses; ↓(r0,w0,r0n,r0,w1,r1) represents an execution of operations on reading 0, writing 0, reading 0 n times, reading 0, writing 1, reading 1 for the storage units in the memory according to the descending order of the addresses; ↓(r1,w1,r1n,r1,w0,r0) represents an execution of operations on reading 1, writing 1, reading 1 n times, reading 1, writing 0, reading 0 for the storage units in the memory according to the descending order of the addresses; ↑↓(r0) represents an execution of operations on reading 0 for the storage units in the memory according to the ascending order or the descending order of the addresses.
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