| CPC G11C 29/12005 (2013.01) [G01R 31/31708 (2013.01)] | 7 Claims |
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1. A printed circuit board (PCB) comprising:
a system on a chip (SOC) comprising at least one processor; and
an interactive DRAM signal analyzer comprising:
a signal input/output unit;
a signal analysis processing unit configured to receive a command signal and data from the SOC through a memory subsystem and generate a calibration command based on an analysis of the command signal and data received from the SOC, wherein the command signal is a signal to request data write or data read at a specific address of DRAM; and
a DRAM model configured to interface with virtual DRAM based on the command signal and data received from the signal analysis processing unit and to output a command signal and data,
wherein the signal analysis processing unit is configured to:
transfer, to the DRAM model, a first command signal and data received from the memory subsystem,
receive a non-calibration command signal and data that are fed back by the DRAM model, generate a first calibration command based on an analysis of the non-calibration command signal and data, and transmit the first calibration command to the memory subsystem, and
transfer, to the DRAM model, a second command signal and data that have been calibrated based on the first calibration command from the memory subsystem,
wherein the first calibration command is related to a calibration of at least one of a phase difference between signals, a voltage level of the signal, and a memory protocol between the signals, and
wherein a ball map of the interactive DRAM signal analyzer is the same as a ball map of an actual DRAM to be placed on the PCB.
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