US 12,308,082 B2
Semiconductor memory devices that support enhanced data recovery operations
Seungjun Oh, Suwon-si (KR); Seong Geon Lee, Suwon-si (KR); Dae-Won Kim, Suwon-si (KR); Kyungduk Lee, Suwon-si (KR); and Youn-Soo Cheon, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 18, 2023, as Appl. No. 18/302,034.
Claims priority of application No. 10-2022-0106203 (KR), filed on Aug. 24, 2022.
Prior Publication US 2024/0071545 A1, Feb. 29, 2024
Int. Cl. G11C 29/12 (2006.01); G06F 11/00 (2006.01); G11C 29/00 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/12005 (2013.01) [G11C 29/42 (2013.01); G11C 2029/1202 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of operating a memory device, comprising:
reading a first page of memory cells containing at least one worn-out memory cell therein using a read voltage, from a first memory block;
reading a second page of memory cells, which extends adjacent to the first page in the first memory block, using the read voltage;
determining a match rate between a position of a column including a “0” bit in the first page with a position of an equivalent column including a “0” bit in the second page, for each of the columns associated with the first and second pages, where the match rate corresponds to a ratio between: (i) a number of columns having matching “0” bits in the first and second pages, and (ii) a number of total columns within the first and second pages; and then
reading the second page by adjusting a read pass voltage applied to a word line of another page in the first memory block, when the match rate exceeds a threshold match rate.