CPC G11C 29/12005 (2013.01) [G11C 29/42 (2013.01); G11C 2029/1202 (2013.01)] | 16 Claims |
1. A method of operating a memory device, comprising:
reading a first page of memory cells containing at least one worn-out memory cell therein using a read voltage, from a first memory block;
reading a second page of memory cells, which extends adjacent to the first page in the first memory block, using the read voltage;
determining a match rate between a position of a column including a “0” bit in the first page with a position of an equivalent column including a “0” bit in the second page, for each of the columns associated with the first and second pages, where the match rate corresponds to a ratio between: (i) a number of columns having matching “0” bits in the first and second pages, and (ii) a number of total columns within the first and second pages; and then
reading the second page by adjusting a read pass voltage applied to a word line of another page in the first memory block, when the match rate exceeds a threshold match rate.
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