US 12,308,079 B2
Shift register, gate driving circuit and display apparatus
Liheng Wei, Beijing (CN); Huijuan Yang, Beijing (CN); Tingliang Liu, Beijing (CN); Yi Zhang, Beijing (CN); Xiaoqing Shu, Beijing (CN); Lingtong Li, Beijing (CN); Maoying Liao, Beijing (CN); and Tianci Chen, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/027,321
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 28, 2022, PCT No. PCT/CN2022/101950
§ 371(c)(1), (2) Date Mar. 20, 2023,
PCT Pub. No. WO2023/178868, PCT Pub. Date Sep. 28, 2023.
Claims priority of application No. PCT/CN2022/082794 (WO), filed on Mar. 24, 2022.
Prior Publication US 2024/0355403 A1, Oct. 24, 2024
Int. Cl. G11C 19/28 (2006.01); G09G 3/20 (2006.01)
CPC G11C 19/28 (2013.01) [G09G 3/20 (2013.01); G09G 2310/0286 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A shift register, comprising:
an input circuit coupled to a signal input terminal, a first clock signal terminal and a third node, and configured to write a signal from the signal input terminal to the third node in response to control of a signal from the first clock signal terminal;
a first control circuit coupled to a first power terminal, a preset control signal terminal, a preset clock signal terminal and a first node, and configured to write a voltage from the first power terminal to the first node in response to control of signals from the preset control signal terminal and the preset clock signal terminal, wherein the first control circuit is directly coupled to the first node, and the preset control signal terminal is the signal input terminal;
a second control circuit coupled to a second power terminal, the signal input terminal and the first node, and configured to write a voltage from the second power terminal to the first node in response to control of the signal from the signal input terminal; and
an output circuit coupled to a signal output terminal, the first power terminal, the second power terminal, the first node and a fourth node, and configured to write the voltage from the second power terminal to the signal output terminal in response to control of a voltage at the first node, and to write the voltage from the first power terminal to the signal output terminal in response to control of a voltage at the fourth node, wherein the third node is coupled to the fourth node.