| CPC G11C 16/3459 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01)] | 11 Claims |
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1. A three-dimensional memory device (100), comprising:
a plurality of memory cell strings (115n,1), each memory cell string comprising a plurality of memory cells (Tk) stacked onto one another on a substrate each one at a respective vertical distance from the substrate;
a plurality of word lines (WLk) each one associated with respective memory cells of the plurality of memory cell strings arranged at a same vertical distance from the substrate; and
a control circuit (135) configured to:
(i) apply a sequence of incremental step programming pulses to a selected memory cell of a reference memory cell string to program the selected memory cell at a target threshold voltage among a plurality of target threshold voltages;
(ii) perform a program verify operation in response to a respective programming pulse after applying a first programming pulse of the sequence of incremental step programming pulses, the first programming pulse is for a start of program verify operations, and is a predefined programming pulse determined by the three-dimensional memory device;
(iii) determine another pulse of the sequence of incremental step programming pulses to be an updated first programming pulse for the selected memory cell and for the target threshold voltage based on a second programming pulse that is a final programming pulse of the sequence of incremental step programming pulses after which a program verify operation determines that the selected memory cell has been programmed at the target threshold voltage; and
(iv) perform the program verify operations starting from the updated first programming pulse for each subsequently-selected memory cell to be programmed at the target threshold voltage, and
associated with the same word line as the selected memory cell.
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