US 12,308,074 B2
Enhanced gradient seeding scheme during a program operation in a memory sub-system
Vinh Q. Diep, Hayward, CA (US); Ching-Huang Lu, Fremont, CA (US); and Yingda Dong, Los Altos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 19, 2023, as Appl. No. 18/545,888.
Application 18/545,888 is a continuation of application No. 17/247,576, filed on Dec. 16, 2020, granted, now 11,901,010.
Prior Publication US 2024/0120010 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a first positive voltage to be applied to a first plurality of word lines of a data block of the memory array during a seeding phase of a program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation;
causing a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage; and
causing a third positive voltage to be applied to one or more third word lines coupled to one or more third memory cells on the source-side of the one or more second memory cells in the string of memory cells during the seeding phase, wherein the third positive voltage is less than the second positive voltage.