US 12,308,072 B2
Integrated scaling and stretching platform for optimizing monolithic integration and/or heterogeneous integration in a single semiconductor die
Chao-Chun Lu, Hsinchu (TW)
Assigned to INVENTION AND COLLABORATION LABORATORY PTE. LTD., Singapore (SG); and ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed by INVENTION AND COLLABORATION LABORATORY PTE. LTD., Singapore (SG); and ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed on Nov. 19, 2021, as Appl. No. 17/531,015.
Claims priority of provisional application 63/276,698, filed on Nov. 8, 2021.
Claims priority of provisional application 63/254,598, filed on Oct. 12, 2021.
Claims priority of provisional application 63/158,896, filed on Mar. 10, 2021.
Prior Publication US 2022/0293170 A1, Sep. 15, 2022
Int. Cl. G11C 11/417 (2006.01); G11C 11/412 (2006.01); H03K 19/17728 (2020.01); H03K 19/1776 (2020.01); H10B 10/00 (2023.01)
CPC G11C 11/417 (2013.01) [G11C 11/412 (2013.01); H03K 19/17728 (2013.01); H03K 19/1776 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A monolithic die, comprising:
a first processing unit circuit formed in the monolithic die with a scanner maximum field area, the first processing unit circuit with a plurality of a first logic cores, and each first logic core corresponding to a first cache memory; and
a second processing unit circuit formed in the monolithic die, the second processing unit circuit with a plurality of a second logic cores, and each second logic core corresponding to a second cache memory;
wherein the scanner maximum field area of the monolithic die is defined by a specific technology node.