US 12,308,070 B2
Word line drivers for multiple-die memory devices
Fatma Arzum Simsek-Ege, Boise, ID (US); and Mingdong Cui, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 5, 2024, as Appl. No. 18/765,076.
Application 18/765,076 is a continuation of application No. 17/893,654, filed on Aug. 23, 2022, granted, now 12,051,459.
Prior Publication US 2025/0006249 A1, Jan. 2, 2025
Int. Cl. G11C 16/10 (2006.01); G11C 11/408 (2006.01); H10B 80/00 (2023.01)
CPC G11C 11/4085 (2013.01) [G11C 11/4087 (2013.01); H10B 80/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first semiconductor die comprising a plurality of word line conductors stacked along a first direction and extending along a second direction, each word line conductor of the plurality of word line conductors operable to access a respective set of one or more memory cells; and
a second semiconductor die comprising:
a doped semiconductor material portion extending along the second direction;
a first gate material portion operable to activate a first channel of the doped semiconductor material portion to couple a first word line conductor of the plurality of word line conductors with a word line decoder signal;
a second gate material portion operable to activate a second channel of the doped semiconductor material portion to couple the first word line conductor with a deselection voltage;
a third gate material portion operable to activate a third channel of the doped semiconductor material portion to couple a second word line conductor of the plurality of word line conductors with the word line decoder signal; and
a fourth gate material portion operable to activate a fourth channel of the doped semiconductor material portion to couple the second word line conductor with the deselection voltage.