US 12,308,069 B2
DRAM with quick random row refresh for rowhammer mitigation
Victor Van Der Veen, Amsterdam (NL); Mosaddiq Saifuddin, San Diego, CA (US); Pankaj Deshmukh, San Diego, CA (US); Behnam Dashtipour, San Diego, CA (US); and David Hartley, Berlin (DE)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 17, 2021, as Appl. No. 17/445,220.
Claims priority of provisional application 63/105,621, filed on Oct. 26, 2020.
Prior Publication US 2022/0129200 A1, Apr. 28, 2022
Int. Cl. G06F 11/00 (2006.01); G11C 11/406 (2006.01); G11C 11/4078 (2006.01)
CPC G11C 11/4078 (2013.01) [G11C 11/40603 (2013.01); G11C 11/40611 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A memory controller for a dynamic random access memory (DRAM) having a plurality of rows, comprising:
a logic circuit configured to identify an issuance of a specific type of command directed to the DRAM, wherein an identification of the issuance of the specific type of command by the logic circuit is independent of the plurality of rows; and
a probability engine configured to generate an integer random number in response to an initial identification of the specific type of command, the probability engine being further configured to increment a count for each successive identification of the specific type of command; and
a command generator configured to command the DRAM to refresh at least one row in response to the count equaling the integer random number.