US 12,308,068 B2
Control circuit and memory
Lu Liu, Hefei (CN); and Jixing Chen, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 16, 2023, as Appl. No. 18/451,069.
Application 18/451,069 is a continuation of application No. PCT/CN2022/129777, filed on Nov. 4, 2022.
Claims priority of application No. 202211247767.5 (CN), filed on Oct. 12, 2022.
Prior Publication US 2024/0127880 A1, Apr. 18, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/406 (2006.01)
CPC G11C 11/40622 (2013.01) [G11C 11/40615 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A control circuit, comprising: a random module and an output module, wherein
a first input terminal of the random module receives a refresh count signal, a second input terminal of the random module receives random data, and a control terminal of the random module is connected to an output terminal of the output module, and the random module is configured to process the refresh count signal and the random data based on a row hammer refresh (RHR) signal output by the output module to obtain and output a random signal; and
a first input terminal of the output module receives the refresh count signal, a second input terminal of the output module is connected to an output terminal of the random module, and the output module is configured to generate and output the RHR signal according to the random signal and the refresh count signal.