US 12,308,067 B2
Memory device having stable self-refresh operation and operating method thereof
Sang Hoon Lee, Gyeonggi-do (KR); Sang Jin Byeon, Gyeonggi-do (KR); and Kyo Yun Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 9, 2023, as Appl. No. 18/107,503.
Claims priority of application No. 10-2022-0111372 (KR), filed on Sep. 2, 2022.
Prior Publication US 2024/0079043 A1, Mar. 7, 2024
Int. Cl. G11C 11/406 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/40626 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a counting circuit configured to generate a counting code by counting a first edge of a reference cycle signal having a given frequency in a self-refresh section;
a temperature code output circuit configured to:
receive a temperature detection code that is synchronized with a second edge of the reference cycle signal,
output the temperature detection code as a temperature application code in response to a toggling of the operation control signal in the self-refresh section, and
output the temperature application code that is initialized out of the self-refresh section;
a signal generation circuit configured to:
compare the counting code and the temperature application code in the self-refresh section, and
generate the operation control signal the toggling of which is controlled based on a result of the comparison; and
a refresh operation circuit configured to perform a refresh operation on a cell array area in response to the toggling of the operation control signal in the self-refresh section.