CPC G11C 11/225 (2013.01) [G06F 11/1068 (2013.01); G06F 12/0246 (2013.01); G06F 12/06 (2013.01); G11C 11/02 (2013.01); G11C 11/165 (2013.01); G11C 11/221 (2013.01); G11C 13/0002 (2013.01); G11C 13/0035 (2013.01); G11C 13/0059 (2013.01); G11C 16/105 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7211 (2013.01)] | 14 Claims |
1. An apparatus comprising:
a memory; and
a memory controller coupled to the memory, wherein the memory controller is to:
request a write to an address of an individual memory bank, wherein the individual memory bank is part of a plurality of memory banks comprising memory bit cells, and wherein the plurality of memory banks is part of the memory;
adjust a number of references by one upon the request;
compare the number of references with a threshold to generate a comparison; and
generate a random number between zero and one in response to the comparison indicating that the number of references is equal to the threshold, wherein the memory controller is to reset the number of references if the number of references is equal to the threshold.
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