| CPC G11B 20/10037 (2013.01) [G11B 20/1423 (2013.01)] | 20 Claims |
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1. An electronic circuit, comprising:
a converter circuit configured to convert an input signal to a digital signal, wherein the converter circuit comprises: a current mode logic (CML) circuit configured to generate a CML signal based on the input signal, and a CML-to-digital converter circuit configured to convert the CML signal to the digital signal; and
a compensation circuit coupled to the converter circuit, the compensation circuit comprising:
a sampling circuit configured to receive the digital signal and generate an output signal, the output signal comprising a stream of bits to be transmitted at a plurality of consecutive clock cycles; and
one or more equalizing circuits coupled to the sampling circuit, each of the one or more equalizing circuits being configured to receive a bit of an output feedback signal at a corresponding one of the consecutive clock cycles and generate a corresponding equalization output,
wherein the sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits.
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