US 12,307,978 B2
Display device and electronic device
Hidetomo Kobayashi, Isehara (JP); and Kouhei Toyotaka, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jan. 16, 2024, as Appl. No. 18/413,254.
Application 18/413,254 is a continuation of application No. 17/411,205, filed on Aug. 25, 2021, granted, now 11,881,177.
Application 17/411,205 is a continuation of application No. 16/810,101, filed on Mar. 5, 2020, granted, now 11,205,387, issued on Dec. 21, 2021.
Application 16/810,101 is a continuation of application No. 15/651,192, filed on Jul. 17, 2017, granted, now 10,586,495, issued on Mar. 10, 2020.
Claims priority of application No. 2016-144075 (JP), filed on Jul. 22, 2016.
Prior Publication US 2024/0265877 A1, Aug. 8, 2024
Int. Cl. G09G 3/3266 (2016.01); G06F 3/041 (2006.01); G09G 3/3233 (2016.01); G09G 3/34 (2006.01); G09G 3/36 (2006.01); H10K 59/121 (2023.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G09G 3/3426 (2013.01); G09G 3/3648 (2013.01); G06F 3/0412 (2013.01); G09G 2300/023 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0439 (2013.01); G09G 2300/0456 (2013.01); G09G 2300/046 (2013.01); G09G 2300/0809 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); H10K 59/1213 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A display device comprising:
a display portion over a substrate,
wherein the display portion comprises a pixel comprising a light-emitting element,
wherein the display portion comprises:
a first semiconductor layer comprising a channel formation region of a first transistor;
a first insulating layer over the first semiconductor layer;
a first conductive layer over the first insulating layer, the first conductive layer comprising a region which functions as a gate electrode of a second transistor;
a second insulating layer over the first conductive layer, the second insulating layer comprising a region which functions as a gate insulating layer of the second transistor;
a second semiconductor layer comprising a channel formation region of the second transistor;
a second conductive layer over the second semiconductor layer, the second conductive layer comprising a region which functions as one of a source electrode and a drain electrode of the second transistor;
a third conductive layer over the second semiconductor layer, the third conductive layer comprising a region which functions as the other of the source electrode and the drain electrode of the second transistor; and
a third insulating layer over the second conductive layer and the third conductive layer,
wherein the first conductive layer comprises a region positioned over a gate electrode of the first transistor,
wherein the light-emitting element comprises a region positioned over the third insulating layer,
wherein one of the second conductive layer and the third conductive layer comprises a region which functions as one electrode of a capacitor,
wherein the substrate has flexibility,
wherein the second semiconductor layer does not comprise a region overlapping with the first semiconductor layer, and
wherein the third conductive layer comprises a region overlapping with the first semiconductor layer.