US 12,307,975 B2
Pixel driving circuit, method for driving pixel driving circuit and display apparatus
Dan Cao, Beijing (CN); Wenhui Gao, Beijing (CN); Yonglin Guo, Beijing (CN); Huijuan Yang, Beijing (CN); and Tiaomei Zhang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/696,425
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Sep. 30, 2022, PCT No. PCT/CN2022/123087
§ 371(c)(1), (2) Date Mar. 28, 2024,
PCT Pub. No. WO2024/065614, PCT Pub. Date Apr. 4, 2024.
Prior Publication US 2025/0046247 A1, Feb. 6, 2025
Int. Cl. G09G 3/3233 (2016.01); G09G 3/32 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/32 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/08 (2013.01); G09G 2330/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A pixel driving circuit, comprising:
a light-emitting device;
a driving transistor configured to generate a current for driving the light-emitting device to emit light according to a data voltage;
a first control circuit configured to conduct a first electrode of the driving transistor to a first node in response to a signal at a first scan signal terminal;
a second control circuit configured to form, in response to signals at a second scan signal terminal and a third scan signal terminal, a current path from the first node to a first initialization signal terminal in a case where the first control circuit conducts the first electrode of the driving transistor to the first node, to allow a threshold voltage of the driving transistor to be input to the first node;
a data writing circuit configured to input the data voltage of a data signal terminal to the first node in response to a signal at a fourth scan signal terminal, to change a voltage of the first node from V1−Vth to Vda;
a third control circuit configured to supply a signal at a second initialization signal terminal to a gate of the driving transistor in response to the signal at the first scan signal terminal, to supply a signal at a third initialization signal terminal to the first electrode of the driving transistor in response to a signal at a fifth scan signal terminal, and to supply a signal at a first power terminal to the first electrode of the driving transistor in response to a signal at a light emission control signal terminal;
a first storage circuit configured to keep a voltage difference between the first node and the first power terminal stable; and
a second storage circuit configured to keep a voltage difference between the first node and the gate of the driving transistor stable, and to change a voltage of the gate of the driving transistor from V1 to Vda+Vth in a case that the voltage of the first node is changed from V1−Vth to Vda, where V1 represents a voltage value of a second initialization signal at the second initialization signal terminal, Vth represents the threshold voltage of the driving transistor, and Vda represents the data voltage loaded onto the data signal terminal.