US 12,307,971 B2
Pixel circuit and display device including the same
Yong Won Lee, Paju-si (KR); and Hyun Soo Lee, Paju-si (KR)
Assigned to LG Display Co., Ltd., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on Dec. 18, 2023, as Appl. No. 18/543,613.
Application 18/543,613 is a division of application No. 17/840,072, filed on Jun. 14, 2022, granted, now 11,908,405.
Claims priority of application No. 10-2021-0089923 (KR), filed on Jul. 8, 2021; and application No. 10-2021-0166802 (KR), filed on Nov. 29, 2021.
Prior Publication US 2024/0119902 A1, Apr. 11, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3291 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3291 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A pixel circuit comprising:
a driving element including a first electrode of the driving element that is connected to a first node to which a pixel driving voltage is applied, a gate electrode of the driving element that is connected to a second node, and a second electrode of the driving element that is connected to a third node, the driving element configured to supply an electric current;
a light emitting element configured to emit light according to the electric current;
a first switch element connected to the gate electrode of the driving element at the second node, the first switch element configured to supply a data voltage to the gate electrode of the driving element according to a first signal received by the first switch element;
a second switch element connected between the light emitting element and the second electrode of the driving element at the third node, the second switch element configured to be turned on according to a second signal received by the second switch element;
a third switch element connected to the second electrode of the driving element and the second switch element at the third node, the third switch element configured to be turned on and supply a reference voltage to the third node according to a third signal received by the third switch element; and
a first capacitor connected to the second node and the third node,
wherein a level of the second signal is opposite of one of a level of the first signal received by the first switch element or a level of the third signal received by the third switch element,
wherein the first signal and the third signal are a same signal.