| CPC G09G 3/3233 (2013.01) [H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0223 (2013.01); G09G 2320/0233 (2013.01)] | 19 Claims |
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1. A pixel driving circuit, comprising:
a driving circuit, coupled to a first node, a second node and a third node, and configured to input a driving current to the third node through the second node according to a signal of the first node;
a control circuit, coupled to a first power terminal, the second node, the third node, a fourth node and an enable signal terminal, and configured to communicate the first power terminal with the second node in response to a signal of the enable signal terminal, and communicate the third node with the fourth node in response to the signal of the enable signal terminal;
a first reset circuit, coupled to the fourth node, a reset signal terminal and an initial signal terminal, and configured to transmit a signal of the initial signal terminal to the fourth node in response to a signal of the reset signal terminal;
a second reset circuit, coupled to the first node, the first power terminal and the reset signal terminal, and configured to transmit a signal of the first power terminal to the first node in response to the signal of the reset signal terminal; and
a coupling circuit, coupled between the first node and the fourth node;
wherein the driving circuit, the control circuit, the first reset circuit and the second reset circuit all comprise transistors, the transistors in the driving circuit, the control circuit, the first reset circuit and the second reset circuit are all N-type transistors, the transistor in the first reset circuit comprises an oxide transistor, and the transistor in the second reset circuit comprises an oxide transistor;
wherein the driving circuit comprises:
a driving transistor, wherein a gate of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node;
the control circuit comprises:
a fifth transistor, wherein a gate of the fifth transistor is coupled to the enable signal terminal, a first electrode of the fifth transistor is coupled to the first power terminal, and a second electrode of the fifth transistor is coupled to the second node; and
a sixth transistor, wherein a gate of the sixth transistor is coupled to the enable signal terminal, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the fourth node;
the first reset circuit comprises:
a first transistor, wherein a gate of the first transistor is coupled to the reset signal terminal, a first electrode of the first transistor is coupled to the initial signal terminal, and a second electrode of the first transistor is coupled to the fourth node;
the second reset circuit comprises:
a second transistor, wherein a gate of the second transistor is coupled to the reset signal terminal, a first electrode of the second transistor is coupled to the first power terminal, and a second electrode of the second transistor is coupled to the first node;
the coupling circuit comprises:
a capacitor, coupled between the first node and the fourth node;
wherein the driving transistor, the first transistor, the second transistor, the fifth transistor and the sixth transistor are the N-type transistors, and the first transistor and the second transistor are the oxide transistors.
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