US 12,307,948 B2
Display substrate, method of manufacturing the same and display device
Miao Wang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/027,308
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 30, 2022, PCT No. PCT/CN2022/102741
§ 371(c)(1), (2) Date Mar. 20, 2023,
PCT Pub. No. WO2024/000376, PCT Pub. Date Jan. 4, 2024.
Prior Publication US 2024/0355265 A1, Oct. 24, 2024
Int. Cl. G09G 3/32 (2016.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC G09G 3/32 (2013.01) [H10D 86/021 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A display substrate, comprising: a plurality of first gate driving circuits and a plurality of second gate driving circuits, wherein a first gate driving signal output by the first gate driving circuit and a second gate driving signal output by the second gate driving circuit have different timing; the first gate driving circuit and the second gate driving circuit share at least one signal line;
wherein the first gate driving circuit and the second gate driving circuit share a first level signal line, and the first level signal line transmits a DC signal having a first level;
wherein the first gate driving circuit and the second gate driving circuit share a first clock signal line and/or a second clock signal line, a phase of a first clock signal transmitted by the first clock signal line is opposite to a phase of a second clock signal transmitted by the second clock signal line;
wherein the first gate driving circuit is coupled to a first frame start signal line, and the second gate driving circuit is coupled to a second frame start signal line;
wherein at least one of the first level signal line, the first clock signal line, the second clock signal line, and the first frame start signal line and the second frame start signal line is made using a second source-drain metal layer in the display substrate; and
wherein at least one of the first level signal line, the first clock signal line, the second clock signal line, the first frame start signal line and the second frame start signal line includes two layers of conductive layers stacked to each other, one layer of conductive layer is made of the second source-drain metal layer, and the other layer of conductive layer is made of a third source-drain metal layer in the display substrate.