US 12,307,942 B2
Scan driver
Hai Jung In, Yongin-si (KR); Min Ku Lee, Yongin-si (KR); and Seung Hee Lee, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on May 13, 2024, as Appl. No. 18/662,918.
Application 18/662,918 is a continuation of application No. 18/086,648, filed on Dec. 22, 2022, granted, now 11,984,058.
Claims priority of application No. 10-2022-0044062 (KR), filed on Apr. 8, 2022.
Prior Publication US 2024/0296777 A1, Sep. 5, 2024
Int. Cl. G09G 3/20 (2006.01); G09G 3/3266 (2016.01)
CPC G09G 3/2092 (2013.01) [G09G 3/3266 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0219 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A stage comprising:
a first input terminal configured to receive an input signal;
a second input terminal configured to receive a first clock signal;
a third input terminal configured to receive a second clock signal;
a fourth input terminal electrically connected to a first node and configured to receive a third clock signal;
a first output terminal electrically connected to a second node and configured to output a first signal;
a second output terminal configured to output a second signal;
an input circuit controlled in response to a voltage of the second input terminal and electrically connected to the first input terminal;
a pull-up transistor including a gate electrode electrically connected to the first input terminal through the input circuit, and configured to switch an electrical connection between the third input terminal and the first output terminal;
a first pull-down transistor including a gate electrode and configured to switch an electrical connection between the first output terminal and a first power input terminal;
a control circuit controlled in response to a voltage that is output from the input circuit and, configured to switch an electrical connection between the gate electrode of the first pull-down transistor and a third node; and
a second pull-down transistor including a gate electrode electrically connected to the third node, and configured to switch an electrical connection between the first output terminal and the first power input terminal.