US 12,307,935 B2
Display control integrated circuit applicable to performing video output generator reset control in display device
Hsueh-Ping Wang, HsinChu (TW); and Chi-Hsiung Cheng, HsinChu (TW)
Assigned to Realtek Semiconductor Corp., HsinChu (TW)
Filed by Realtek Semiconductor Corp., HsinChu (TW)
Filed on Mar. 15, 2022, as Appl. No. 17/695,811.
Claims priority of application No. 110136927 (TW), filed on Oct. 4, 2021.
Prior Publication US 2023/0106022 A1, Apr. 6, 2023
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/20 (2013.01) [G09G 2300/0408 (2013.01); G09G 2300/0814 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display device, applicable to performing video output generator reset control according to a reset signal, the display device comprising:
a display output module for displaying a plurality of images; and
a display control integrated circuit (IC), arranged to receive a video input signal comprising a video stream and generate video data according to the video input signal, comprising:
an image processing circuit, comprising:
a video output generator, arranged to generate an input vertical synchronization signal for controlling playback of the video data, the input vertical synchronization signal generated according to a first periodic signal having a frequency according to a frame rate of the video stream, and when the reset signal is received, the video output generator is arranged to control timing of a pulse of the input vertical synchronization signal according to the reset signal; and
a display output control circuit, coupled to the video output generator, wherein the display output control circuit generates a set of display control signals to control the display output module within the display device to perform display operations, and the set of display control signals includes a display clock signal and a single display vertical synchronization signal for being used as timing reference of a timing controller within the display output module, the single vertical synchronization signal generated according to a second periodic signal being a frequency-divided signal of the display clock signal and having a frequency according to a display refresh rate of the display output module, and the display output control circuit generates the reset signal according to a comparison of timing of a plurality of pulses carried by the single display vertical synchronization signal, comprising:
generating a plurality of second counting results according to the second periodic signal; and
when any second counting result among the plurality of second counting results matches a third predetermined counter value, generating and outputting the reset signal to the video output generator;
wherein the third predetermined counter value corresponds to a predetermined timing ratio, during a time interval between a first time point and a second time point at which two consecutive pulses among the plurality of pulses carried by the single display vertical synchronization signal respectively appear, the display output control circuit generates and outputs the reset signal to the video output generator at an intermediate time point between the two consecutive pulses corresponding to the predetermined timing ratio, the video output generator triggers a pulse of the input vertical synchronization signal at the intermediate time point in response to receiving the reset signal, and the triggered pulse of the input vertical synchronization signal makes timing of the input vertical synchronization signal be associated with timing of the single display vertical synchronization signal, wherein the first time point is earlier than the second time point and the video output generator associates timing of the input vertical synchronization signal with timing of the single display vertical synchronization signal in response to the reset signal.