US 12,307,547 B2
Apparatus and method for performing a stable and short latency sorting operation
Saikat Mandal, Sacramento, CA (US); Prasoonkumar Surti, Folsom, CA (US); and Sven Woop, Voelklingen (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 6, 2024, as Appl. No. 18/433,823.
Application 18/433,823 is a continuation of application No. 16/823,741, filed on Mar. 19, 2020, granted, now 11,900,498.
Prior Publication US 2024/0265487 A1, Aug. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 1/60 (2006.01); G06F 7/02 (2006.01); G06F 7/24 (2006.01); G06F 7/505 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06T 1/20 (2006.01); G06T 15/00 (2011.01); G06T 15/08 (2011.01); G06T 17/10 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 7/02 (2013.01); G06F 7/24 (2013.01); G06F 7/505 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/3885 (2013.01); G06T 15/005 (2013.01); G06T 15/08 (2013.01); G06T 17/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor and non-transitory machine-readable medium having program code stored thereon which, when executed by the processor, causes the processor to perform:
receiving a first plurality of input values to be sorted into a sorted order, wherein the first plurality of input values are obtained within a graphics pipeline stage,
comparing each input value within the first plurality of input values with all other input values within the first plurality of input values to generate a second plurality of comparison result values;
generating a result matrix with a row associated with each input value within the first plurality of input values, a plurality of bits in each row comprising comparison result values indicating results of comparisons the each input value with other input values within the first plurality of input values, wherein a first region of the result matrix is to store a first set of bits comprising the second plurality of comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the second plurality of comparison result values;
performing additions of the bits in each row of the result matrix to generate a corresponding first plurality of sum results; and
sorting the corresponding first plurality of sum results to return the sorted order to the graphics pipeline stage.