US 12,307,281 B2
Virtual machine migration based on power utilization
Parminder Singh Sethi, Ludhiana (IN); Suren Kumar, Bangalore (IN); and Durai S. Singh, Chennai (IN)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Mar. 15, 2022, as Appl. No. 17/695,446.
Prior Publication US 2023/0297402 A1, Sep. 21, 2023
Int. Cl. G06F 9/455 (2018.01); G06F 9/50 (2006.01)
CPC G06F 9/45558 (2013.01) [G06F 9/5094 (2013.01); G06F 2009/4557 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
retrieving power utilization data of a plurality of host devices;
identifying at least one virtual machine for migration from a source host device to a target host device of the plurality of host devices;
predicting power utilization of the at least one virtual machine;
determining the target host device based, at least in part, on the power utilization data of the plurality of host devices and the predicted power utilization of the at least one virtual machine; and
migrating the at least one virtual machine from the source host device to the target host device;
wherein the predicting of the power utilization of the at least one virtual machine comprises:
identifying at least one resource utilization value of the at least one virtual machine;
comparing the at least one resource utilization value of the at least one virtual machine to a mapping of virtual machine resource utilization values to virtual machine power utilization values; and
determining the predicted power utilization of the at least one virtual machine based, at least in part, on the mapping of the virtual machine resource utilization values to the virtual machine power utilization values;
wherein the determining of the predicted power utilization of the at least one virtual machine based, at least in part, on the mapping is performed as a function of one or morn configuration differences between the at least one virtual machine and one or more other virtual machines of at least one of the host devices; and
wherein the steps of the method are executed by a processing device operatively coupled to a memory.