US 12,307,002 B2
Register shielding in semiconductor devices
Salvatore Marco Rosselli, Catania (IT); and Giuseppe Guarnaccia, San Gregorio di Catania (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed on Aug. 5, 2022, as Appl. No. 17/882,400.
Claims priority of application No. 102021000021944 (IT), filed on Aug. 17, 2021.
Prior Publication US 2023/0055842 A1, Feb. 23, 2023
Int. Cl. G06F 21/76 (2013.01); G06F 21/60 (2013.01); G06F 21/74 (2013.01); G06F 21/79 (2013.01)
CPC G06F 21/76 (2013.01) [G06F 21/604 (2013.01); G06F 21/74 (2013.01); G06F 21/79 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a set of registers, which, in operation, store digital data;
an interface coupled to the set of registers, wherein the interface, in operation, receives external requests to access registers of the set of registers; and
selectively-activateable register shield circuitry, coupled between the interface and the set of registers, wherein the register shield circuitry, in response to activation, in operation:
intercepts requests received by the interface and directed to a register of the set of registers;
determines whether an intercepted request is directed to a portion of a register of the set of registers to which access is prohibited; and
responds to a determination that the intercepted request is directed to a portion of a register of the set of registers to which access is prohibited by preventing access to data stored in the portion of the register of the set of registers, wherein the preventing access to data stored in the portion of the register of the set of registers comprises applying a bit masking pattern to data returned in response to the request for access.