US 12,306,948 B2
Baseboard management controller module
Lin Zhang, Shenzhen (CN); Wen-Xiao Lu, Shenzhen (CN); Hui-Bo Liu, Shenzhen (CN); and Zhi-Yu Deng, Shenzhen (CN)
Assigned to Shenzhen Fulian Fugui Precision Industry Co., Ltd., Shenzhen (CN)
Filed by Shenzhen Fulian Fugui Precision Industry Co., Ltd., Shenzhen (CN)
Filed on Jun. 27, 2022, as Appl. No. 17/850,034.
Claims priority of application No. 202210414880.1 (CN), filed on Apr. 15, 2022.
Prior Publication US 2023/0334155 A1, Oct. 19, 2023
Int. Cl. G06F 21/57 (2013.01); G06F 13/40 (2006.01); G06F 21/55 (2013.01); G06F 21/73 (2013.01); G06F 21/85 (2013.01)
CPC G06F 21/572 (2013.01) [G06F 13/4022 (2013.01); G06F 13/4027 (2013.01); G06F 21/554 (2013.01); G06F 21/73 (2013.01); G06F 21/85 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A baseboard management controller (BMC) module comprising:
a BMC configured for outputting an alarm signal; and
a chip selection module comprising N chip selection units; wherein the chip selection unit is configured for outputting the alarm signal to an external motherboard connected to the data center security control module, wherein N is an integer greater than 1; and
a control module configured for obtaining a motherboard type of the external motherboard and outputting a control signal to the chip selection module according to the motherboard type to start the chip selection unit associated with the motherboard type;
wherein the chip selection module comprises a first multiplexer and a second multiplexer, the first multiplexer comprises a first selection end, a first input end, a first output end and a second output end, the second multiplexer comprises a second selection end, a second input end, a third output end and a fourth output end; the first input end of the first multiplexer is connected to a first port of the BMC, the first output end of the first multiplexer is connected to the second input end of the second multiplexer; the second output end of the first multiplexer is connected to the fourth output end of the second multiplexer; the third output end of the second multiplexer is connected to a first end of an integrated south bridge on the third platform motherboard; and the fourth output end of the second multiplexer is connected to a second end of the integrated south bridge.