US 12,306,902 B2
Hardware acceleration for computing eigenpairs of a matrix
Tomasz J. Nowicki, Fort Montgomery, NY (US); Oguzhan Murat Onen, Boston, MA (US); Tayfun Gokmen, Briarcliff Manor, NY (US); Vasileios Kalantzis, White Plains, NY (US); Chai Wah Wu, Hopewell Junction, NY (US); Mark S. Squillante, Greenwich, CT (US); Malte Johannes Rasch, Chappaqua, NY (US); Wilfried Haensch, Somers, NY (US); and Lior Horesh, North Salem, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 30, 2021, as Appl. No. 17/245,801.
Prior Publication US 2022/0366005 A1, Nov. 17, 2022
Int. Cl. G06F 17/16 (2006.01); G06N 3/065 (2023.01)
CPC G06F 17/16 (2013.01) [G06N 3/065 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a processor; and
a resistive processing unit coupled to the processor, the resistive processing unit comprising an array of cells, the cells comprising respective resistive devices, the resistive devices comprising resistances that are tunable to encode values of a matrix that is storable in the array of cells;
wherein the processor executes program instructions to:
store the matrix in the resistive processing unit by tuning resistances of respective resistive devices of at least a portion of the array of cells to encode values of the matrix in the resistive processing unit; and
utilize the resistive processing unit to determine an eigenvector of the stored matrix by executing a process which comprises performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.