	US 12,306,773 B2
	Multiprocessor system with improved secondary interconnection network
Carl S. Dobbs, Austin, TX (US); and Michael R. Trocino, Austin, TX (US)
Assigned to HyperX Logic, Inc., Austin, TX (US)
Filed by Coherent Logix, Incorporated, Austin, TX (US)
Filed on Sep. 8, 2023, as Appl. No. 18/243,943.
Application 18/243,943 is a continuation of application No. 16/928,611, filed on Jul. 14, 2020, granted, now 11,755,504.
Application 16/928,611 is a continuation of application No. 16/252,827, filed on Jan. 21, 2019, granted, now 10,747,689, issued on Aug. 18, 2020.
Application 16/252,827 is a continuation of application No. 15/437,343, filed on Feb. 20, 2017, granted, now 10,185,672, issued on Jan. 22, 2019.
Application 15/437,343 is a continuation of application No. 15/043,905, filed on Feb. 15, 2016, granted, now 9,612,984, issued on Apr. 4, 2017.
Application 15/043,905 is a continuation of application No. 14/086,648, filed on Nov. 21, 2013, granted, now 9,292,464, issued on Mar. 22, 2016.
Claims priority of provisional application 61/736,851, filed on Dec. 13, 2012.
Prior Publication US 2024/0256472 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/40 (2006.01); G06F 9/4401 (2018.01); G06F 13/16 (2006.01); G06F 13/362 (2006.01); G06F 13/42 (2006.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01)

CPC G06F 13/1652 (2013.01) [G06F 9/4401 (2013.01); G06F 13/362 (2013.01); G06F 13/4022 (2013.01); G06F 13/4027 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 15/17381 (2013.01); G06F 15/7817 (2013.01); G06F 15/7882 (2013.01); Y02D 10/00 (2018.01)]

20 Claims

1. A method, comprising:

establishing a communication path on a primary interconnection network formed by a plurality of routers included in a multi-processor system that includes a plurality of processors coupled to the plurality of routers in an interspersed fashion, wherein the communication path identifies a subset of the plurality of routers;

receiving, by a bus controller, a response via a secondary interconnection network, wherein the response is responsive to a message from a first processor of the plurality of processors;

sending, by the bus controller, the response to a processor interface unit coupled to the bus controller;

by the processor interface unit:

in response to being sent the response, checking the response for an initialization command;

in response to a determination that the response includes the initialization command, comparing an address associated with the response to a hard-wired address associated with the processor interface unit; and

relaying the response to a first router of the plurality of routers; and

sending, by the first router, the response to the first processor via the primary interconnection network.