CPC G06F 12/1458 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/1441 (2013.01)] | 12 Claims |
1. An integrated chip, comprising:
an application processor, configured to send, in a normal secure mode, first data to a storage controller to prompt the storage controller to write the first data into a first address of an off-chip memory;
a security processor, configured to send, in an enhanced secure data exchange mode, a first read instruction to the storage controller to prompt the storage controller to read the first data at the first address and to send the first data to the security processor; and
wherein:
in a normal secure data exchange mode, the application processor prompts, retrieves and reads processed data from the off-chip memory via the storage controller and in an enhanced secure mode, the security processor receives data retrieved by the storage controller; and
after writing the processed data into the off-chip memory via the storage controller, the security processor is configured notify, in an interrupt manner, the application processor to read the processed data.
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