US 12,306,767 B2
Data transfer encryption mechanism
Marcin Andrzej Chrapek, Zurich (CH); and Reshma Lal, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 19, 2022, as Appl. No. 17/968,989.
Prior Publication US 2024/0134804 A1, Apr. 25, 2024
Prior Publication US 2024/0232097 A9, Jul. 11, 2024
Int. Cl. G06F 12/1027 (2016.01); G06F 12/0882 (2016.01); G06F 12/14 (2006.01)
CPC G06F 12/1027 (2013.01) [G06F 12/0882 (2013.01); G06F 12/1408 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the plurality of physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.