| CPC G06F 12/0891 (2013.01) [G06F 2212/604 (2013.01)] | 13 Claims |
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1. A cache system operable to cache data stored in memory for a processor, the cache system comprising:
a cache operable to cache data that is stored in the memory in uncompressed form, and to cache in decompressed form data for compression blocks that is stored in the memory in compressed form; and
an eviction circuit configured to, when it is desired to evict a cache entry from the cache:
select the cache entry to evict from the cache by:
determining age indicating information for each cache entry that could be evicted from the cache; and
selecting the cache entry to evict using the determined age indicating information;
wherein
for each cache entry that caches in decompressed form data for a compression block that is stored in the memory in compressed form, the age indicating information indicates an age of the compression block that the respective cache entry caches data for; and
wherein for each cache entry that caches data that is stored in the memory in uncompressed form, the age indicating information indicates an age of the respective cache entry; and
evict the selected cache entry from the cache.
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