US 12,306,762 B1
Deny list for a memory prefetcher circuit
Tyler J. Huberty, Sunnyvale, CA (US); Eric J. Furbish, Austin, TX (US); Mridul Agarwal, Saratoga, CA (US); Peter G. Soderquist, Natick, MA (US); Sandeep Gupta, Santa Clara, CA (US); Stephen G. Meier, Los Altos, CA (US); Vivek Venkatraman, Sunnyvale, CA (US); Yanran Yang, Mountain View, CA (US); Sahil Kapoor, Sunnyvale, CA (US); and Chandan Shantharaj, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 24, 2023, as Appl. No. 18/323,283.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0862 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 2212/602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a cache memory circuit configured to store information retrieved from a lower-level memory;
a prefetcher circuit configured to generate a prefetch request for a particular prefetch address; and
a prefetch deny list circuit, including a plurality of entries, configured to:
in response to an indication from the cache memory circuit that a previously prefetched address was evicted untouched, allocate, in the plurality of entries, a given entry for the previously prefetched address;
determine whether a particular address for a particular prefetch request corresponds to an active one of the plurality of entries; and
in response to a determination that a particular entry corresponding to the particular address is active, deny the particular prefetch request.