| CPC G06F 12/0223 (2013.01) | 20 Claims |
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1. A data storage device comprising:
a memory; and
one or more processors, individually or in combination, configured to:
receive a new write command from a host, wherein a start or end logical block address (LBA) of the new write command is non-sequential with respect to an end or start LBA, respectively, of a previously-received write command;
determine whether the start or end LBA of the new write command is within a dynamic jump range with respect to the end or start LBA, respectively, of the previously-received write command, wherein the dynamic jump range is based on a history of a plurality of previously-received write commands received from the host; and
in response to determining that the start or end LBA of the new write command is within the dynamic jump range with respect to the end or start LBA, respectively, of the previously-received write command:
process the new write command as a sequential write command by writing data from the new write command in a region in the memory;
determine whether the region in the memory was previously at least partially written in by one of the plurality of previously-received write commands:
in response to determining that the region in the memory was at least partially written in by the one of the plurality of previously-received write commands, decrement a frequency counter; and
in response to determining that the region in the memory was not at least partially written in by the one of the plurality of previously-received write commands, increment the frequency counter:
wherein the dynamic jump range is dynamically determined based on a value of the frequency counter.
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