| CPC G06F 11/1443 (2013.01) [G06F 13/4221 (2013.01); G06F 2201/86 (2013.01); G06F 2213/0026 (2013.01)] | 19 Claims |
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1. A system, comprising:
a communication device including a bus controller configured to manage a Peripheral Component Interconnect Express (PCIe) port, and a link layer reliability (LLR) circuit configured to provide resilience to a PCIe link established on the PCIe port; and
a peer device coupled to the PCIe link,
wherein the LLR circuit is further configured to:
track transactions received from the peer device via the PCIe link using a sequence number counter;
receive a link down indication from the bus controller that a link down event has occurred on the PCIe link;
prevent the link down event from triggering a reset to configuration space registers for the PCIe link;
instruct the bus controller to restore the PCIe link on the PCIe port;
receive an indication from the PCIe port that the PCIe link has been restored; and
send a first control packet on the PCIe link to the peer device, the first control packet including a retry request and an expected sequence number associated with a transaction that the peer device was expecting when the PCIe link went down, the expected sequence number being based on the sequence number counter; and
wherein the peer device is further configured to:
upon receiving the retry request, send a second control packet on the PCIe link to the communication device, the second control packet including a retry acknowledgement and the expected sequence number to the communication device; and
send a protocol packet on the PCIe link to the communication device, the protocol packet including payload data for the transaction associated with the expected sequence number.
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