US 12,306,716 B2
Error coalescing
John Eric Linstadt, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Oct. 30, 2023, as Appl. No. 18/497,161.
Application 18/497,161 is a continuation of application No. 18/070,732, filed on Nov. 29, 2022, granted, now 11,836,044.
Application 18/070,732 is a continuation of application No. 17/363,622, filed on Jun. 30, 2021, granted, now 11,544,145, issued on Jan. 3, 2023.
Application 17/363,622 is a continuation of application No. 16/870,587, filed on May 8, 2020, granted, now 11,080,137, issued on Aug. 3, 2021.
Claims priority of provisional application 62/845,762, filed on May 9, 2019.
Prior Publication US 2024/0241791 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1076 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
first data steering circuitry configurable to exchange at least one bit location in a check symbol location with a corresponding respective at least one bit location in a data symbol location to form a first error coalesced codeword, the first data steering circuitry to output the first error coalesced codeword.