US 12,306,711 B2
Dynamically configurable memory error control schemes
Craig E. Hampel, Los Altos, CA (US); and John Eric Linstadt, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Appl. No. 18/036,246
Filed by Rambus Inc., San Jose, CA (US)
PCT Filed Nov. 16, 2021, PCT No. PCT/US2021/059492
§ 371(c)(1), (2) Date May 10, 2023,
PCT Pub. No. WO2022/119704, PCT Pub. Date Jun. 9, 2022.
Claims priority of provisional application 63/121,131, filed on Dec. 3, 2020.
Prior Publication US 2024/0012709 A1, Jan. 11, 2024
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1008 (2013.01) [G06F 11/10 (2013.01); G06F 11/1044 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory buffer device, comprising:
a first host interface to receive a first memory transaction request that includes a first virtual machine identification indicator and to receive a second memory transaction request that includes a second virtual machine identification indicator;
circuitry to, based on the first virtual machine identification indicator, associate the first memory transaction request with a first memory error resiliency policy and to, based on the second virtual machine identification indicator, associate the second memory transaction request with a second memory error resiliency policy;
circuitry to, based on the first memory transaction request and the first memory error resiliency policy, produce first data having the first memory error resiliency policy, and to, based on the second memory transaction request and the second memory error resiliency policy, produce second data having the second memory error resiliency policy; and
a memory device interface to communicate the first data having the first memory error resiliency policy with a first memory device, and to communicate the second data having the second memory error resiliency policy with the first memory device.