US 12,306,687 B2
Apparatus and method for achieving deterministic power saving state
Nagabhushan Reddy, Bangalore (IN); Abhinay Gupta, Gwalior (IN); Vinithra Janarthanan, Bangalore (IN); Santhosh Raghuram Krishnaswamy, Bangalore (IN); Pannerkumar Rajagopal, Bangalore (IN); Siddharth Selvaraj, Coimbatore (IN); Mihir Shah, Folsom, CA (US); and Vishwanath Somayaji, Haralur Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,335.
Prior Publication US 2022/0011842 A1, Jan. 13, 2022
Int. Cl. G06F 1/32 (2019.01); G06F 1/30 (2006.01); G06F 1/3225 (2019.01); G06F 11/07 (2006.01)
CPC G06F 1/30 (2013.01) [G06F 1/3225 (2013.01); G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/079 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first circuitry to perform, in response to a first message from an operating system, a first process to place a computer device in a first operating mode, store state information in a volatile memory of the computer device, and start a timer for a time-out period for performing the first process, wherein the first process comprises placing first components of the computer device in a low power state, the first components excluding the volatile memory, and the volatile memory is operational in the first operating mode;
a second circuitry to detect, after expiration of the time-out period, a failure of the first process by detecting a failure of one of the first components to enter the low power state; and
a third circuitry to perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device, wherein the second process comprises placing second components of the computer device in a low power state, and the volatile memory is in a low power state in the second operating mode.