US 12,306,663 B2
Systems, methods and apparatus for synchronization of multiple processing devices
Bruce A. Boettjer, Arlington, VA (US); Dennis Kanarsky, Arlington, VA (US); Douglas M. McIntosh, Arlington, VA (US); Hyunsuk Shin, Arlington, VA (US); Forrest B. Lee, Arlington, VA (US); and Robert Horton, Arlington, VA (US)
Assigned to The Boeing Company, Arlington, VA (US)
Filed by The Boeing Company, Arlington, VA (US)
Filed on Mar. 24, 2023, as Appl. No. 18/189,963.
Prior Publication US 2024/0319763 A1, Sep. 26, 2024
Int. Cl. G06F 1/12 (2006.01)
CPC G06F 1/12 (2013.01) 20 Claims
OG exemplary drawing
 
1. A system that comprises:
a memory device configured to store instructions and data;
processing devices distinct from and in communication with the memory device, wherein each of the processing devices comprises respectively:
an internal cache memory;
an adaptable engine that comprises programmable logic configured to form customized memory hierarchies within each of the processing devices;
more than one dual processing cores, wherein at least a first dual processing core, respectively in each processing device is configured to execute advanced reduced instruction set computing of the instructions at independent rates aligned on a transactional step basis;
a peripheral component interconnect express bus restricted to communications with a voting integrated circuit coupled to the memory device, wherein the voting integrated circuit is configured to receive, respectively output data from a transaction on each of the processing devices and to vote between the output data; and
determine whether a plurality of the output data is identical, wherein the voting integrated circuit is implemented in a field programmable gate array (FPGA).