| CPC G03F 7/70633 (2013.01) | 15 Claims |
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1. A method for overlay control based on a semiconductor device pattern, the method being implemented using a system and comprising:
obtaining a selected area from the semiconductor device pattern, the semiconductor device pattern including a wiring pattern section with a first pattern image and a second pattern image that are images of two wiring patterns formed in different steps in a semiconductor fabrication process;
obtaining two overlay errors respectively for two different locations associated with the first pattern image and the second pattern image;
calculating a calibration dimension based on either the overlay errors or a pre-set value; and
generating a calibration image with one dimension thereof equaling the calibration dimension, and generating a calibrated area based on the selected area and the calibration image.
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