CPC G02F 1/1368 (2013.01) [G02F 1/133357 (2021.01); G02F 1/133512 (2013.01); G02F 1/133514 (2013.01); G02F 1/13439 (2013.01); G02F 1/136286 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01)] | 19 Claims |
1. An array substrate, wherein the array substrate comprises a first base substrate, and a drive circuit layer, a transmissive electrode layer and a reflective electrode layer which are sequentially laminated on the first base substrate; wherein
the drive circuit layer comprises a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines extend in a first direction, the plurality of data lines extend in a second direction, and the plurality of gate lines and the plurality of data lines intersect to define a plurality of pixel regions;
wherein each of the pixel regions comprises a transmissive region and a reflective region, and the transmissive region in at least one of the pixel regions comprises at least one first region and at least one second region that are connected to each other, wherein the first region is between adjacent two reflective regions in the first direction and a length direction of the first region is the same as the second direction, and the second region is between adjacent two reflective regions in the second direction and a length direction of the second region is the same as the first direction;
the reflective electrode layer comprises a plurality of reflective electrodes, wherein the plurality of reflective electrodes are in one-to-one correspondence with a plurality of reflective regions and cover the corresponding reflective regions, respectively; and
the transmissive electrode layer comprises a plurality of transmissive electrodes, wherein the plurality of transmissive electrodes are in one-to-one correspondence with a plurality of transmissive regions, and each of the transmissive electrodes at least covers the corresponding transmissive region.
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