US 12,306,509 B2
Array substrate and display panel
Lizhong Wang, Beijing (CN); Guangcai Yuan, Beijing (CN); Ce Ning, Beijing (CN); Jianbo Xian, Beijing (CN); Liping Lei, Beijing (CN); Chunping Long, Beijing (CN); Yunping Di, Beijing (CN); Binbin Tong, Beijing (CN); and Zhen Zhang, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/574,261
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jan. 10, 2023, PCT No. PCT/CN2023/071591
§ 371(c)(1), (2) Date Dec. 26, 2023,
PCT Pub. No. WO2023/134674, PCT Pub. Date Jul. 20, 2023.
Claims priority of application No. 202210041921.7 (CN), filed on Jan. 14, 2022.
Prior Publication US 2024/0241415 A1, Jul. 18, 2024
Int. Cl. G02F 1/1368 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/1368 (2013.01) [G02F 1/136222 (2021.01); G02F 1/136286 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An array substrate comprising:
a base substrate;
a gate line and a data line that are arranged on the base substrate, wherein the gate line intersects the data line to define a pixel region;
a metal oxide thin film transistor is arranged in the pixel region, and the metal oxide thin film transistor comprises a metal oxide semiconductor layer;
the metal oxide semiconductor layer comprises a first part and a second part which are connected with each other, the first part is connected to the data line through a first via hole, the first part is in a stripe shape, and a first included angle is between an extension direction of the first part and an extension direction of the data line, and the first included angle is greater than 0 degree and less than or equal to 90 degrees;
an orthographic projection of the second part on the base substrate overlaps with an orthographic projection of the gate line on the base substrate and does not overlap with an orthographic projection of the data line on the base substrate; and
a shape of the metal oxide semiconductor layer on a plane parallel to a main surface of the base substrate is a zigzag line, and a planar shape of a closed area formed by intersection of an orthographic projection of the metal oxide semiconductor layer, the orthographic projection of the data line and the orthographic projection of the gate line on the base substrate is a rectangle or a right trapezoid;
a width of the first part in the extension direction of the data line ranges from 10% to 50% of a width of the second part in an extension direction of the gate line, and an area of the first part ranges from 10% to 30% of an area of the second part.